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1 ? fn7450.1 el9111, EL9112 triple differential receiver/equalizer the el9111 and EL9112 are triple channel differential receivers and equalizers. they contains three high speed differential receivers with five programmable poles. the outputs of these pole blocks ar e then summed into an output buffer. the equalization length is set with the voltage on a single pin. the el9111 and EL9112 also contain a 3-statable output, enabling multiple devices to be connected in parallel and used in a multiplexing application. the gain can be adjusted up or down on each channel by 6db using its v gain control signal. in addition, a further 6db of gain can be switched in to provide a matched drive into a cable. the el9111 and EL9112 have a bandwidth of 150mhz and consume just 108ma on 5v supply. a single input voltage is used to set the compensation levels for the required length of cable. the el9111 is a special version of the EL9112 that decodes syncs encoded onto the common modes of three pairs of cat-5 cable by the el4543. (ref er to the el4543 datasheet for details.) the el9111 and EL9112 are available in a 28-pin qfn package and are specified for o peration over the full -40c to +85c temperature range. features ? 150mhz -3db bandwidth ? cat-5 compensation - 50mhz @ 1000 ft - 125mhz @ 500 ft ? 108ma supply current ? differential input range 3.2v ? common mode input range -4v to +3.5v ? 5v supply ? output to within 1.5v of supplies ? available in 28-pin qfn package ? pb-free available (rohs compliant) applications ? twisted-pair receiving/equalizer ? kvm (keyboard/video/mouse) ? vga over twisted-pair ? security video pinouts el9111 (28-pin qfn) top view EL9112 (28-pin qfn) top view thermal pad 22 21 20 19 18 17 16 28 27 26 25 24 9 10 11 12 13 1 2 3 4 5 6 7 vsmo_b vout_b vspo_b vspo_g vout_g vsmo_g vsmo_r vsp vinm_b vinp_b vinm_g vinp_g vinm_r vinp_r 0v enable x2 syncref vout vspo_r vctrl vref vgain_r vgain_g 8 15 14 23 vsm vgain_b vout_r hout thermal pad 22 21 20 19 18 17 16 28 27 26 25 24 9 10 11 12 13 1 2 3 4 5 6 7 vsmo_b vout_b vspo_b vspo_g vout_g vsmo_g vsmo_r vsp vinm_b vinp_b vinm_g vinp_g vinm_r vinp_r 0v enable x2 vcm_b vcm_g vspo_r vctrl vref vgain_r vgain_g 8 15 14 23 vsm vgain_b vout_r vcm_r data sheet caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. may 17, 2005
2 fn7450.1 may 17, 2005 ordering information part number package tape & reel pkg. dwg. # part number package tape & reel pkg. dwg. # el9111il 28-pin qfn - mdp0046 EL9112il 28-pin qfn - mdp0046 el9111il-t7 28-pin qfn 7? mdp0046 EL9112il-t7 28-pin qfn 7? mdp0046 el9111il-t13 28-pin qfn 13? mdp0046 EL9112il-t13 28-pin qfn 13? mdp0046 el9111ilz (note) 28-pin qfn (pb-free) - mdp0046 EL9112ilz (note) 28-pin qfn (pb-free) - mdp0046 el9111ilz-t7 (note) 28-pin qfn (pb-free) 7? mdp0046 EL9112ilz-t7 (note) 28-pin qfn (pb-free) 7? mdp0046 el9111ilz-t13 (note) 28-pin qfn (pb-free) 13? mdp0046 EL9112ilz-t13 (note) 28-pin qfn (pb-free) 13? mdp0046 note: intersil pb-free products employ special pb-free material se ts; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb- free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. el9111, EL9112
3 fn7450.1 may 17, 2005 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maxi mum ratings (t a = 25c) supply voltage between v s + and v s - . . . . . . . . . . . . . . . . . . . . .12v maximum continuous output current per channel. . . . . . . . . 30ma power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . v s - -0.5v to v s + +0.5v storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c die junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v sa + = v a + = +5v, v sa - = v a - = -5v, t a = 25c, unless otherwise specified. parameter description conditions min typ max unit ac performance bw bandwidth (see figure 1) 150 mhz sr slew rate v in = -1v to +1v, v g = 0.39, v c = 0, r l = 75 + 75 ? 1.5 kv/s thd total harmonic distortion 10mhz 2v p-p out, v g = 1v, x2 gain, v c = 0 -50 dbc dc performance v(v out ) os offset voltage x2 = high, no equalization -110 -10 +78 mv ? v os channel-to-channel offset matching x2 = high, no equalization -100 0 +100 mv input characteristics cmir common-mode input range -4/+3.5 v o noise output noise v g = 0v, v c = 0v, x2 = high, r load = 150 ?, input 50 ? to gnd, 10mhz -110 dbm cmrr common-mode rejection ratio measured at 10khz -80 db cmrr common-mode rejection ratio measured at 10mhz -55 db cmbw cm amplifier bandwidth 10k || 10pf load 50 mhz cm slew cm slew rate measured @ +1v to -1v 100 v/s c indiff differential input capacitance capacitance v inp to v inm 600 ff r indiff differential input resistance resistance v inp to v inm 12.4 m ? c incm cm input capacitance capacitance v inp = v inm to gnd 1.2 pf r incm cm input resistance resistance v inp = v inm to gnd 1 2.8 m ? +i in positive input current dc bias @ v inp = v inm = 0v 1 a -i in negative input current dc bias @ v inp = v inm = 0v 1 a v indiff differential input range v inp - v inm when slope gain falls to 0.9 2.5 3.2 v output characteristics v(v out ) output voltage swing r l = 150 ? 3.5 v i(v out ) output drive current r l = 10 ? , v inp = 1v, v inm = 0v, x2 = high, v g = 0.39 50 60 ma r(v cm ) cm output resistance of vcm_r/g/b (EL9112 only) at 100khz 30 ? gain gain v c = 0, v g = 0.39, x2 = 5, r l = 150 ? 0.85 1.0 1.1 ? gain channel-to-channel gain matching v c = 0, v g = 0.39, x2 = 5, r l = 150 ? 36% v(sync) hi high level output on v/h out (el9111 only) v(v sp ) - 0.1v v(v sp ) el9111, EL9112
4 fn7450.1 may 17, 2005 v(sync) lo low level output on v/h out (el9111 only) 0v(sync ref) + 0.1v supply i son supply current per channel v enbl = 5, v inm = 0 323639ma i soff supply current per channel v enbl = 0, v inm = 0 0.2 0.4 ma psrr power supply rejection ratio dc to 100khz, 5v supply 65 db logic control pins (enable, x2) v hi logic high level v in - v logic ref for guaranteed high level 1.35 v v low logic low level v in - v logic ref for guaranteed low level 0.8 v i logich logic high input current v in = 5v, v logic = 0v 50 a i logicl logic low input current v in = 0v, v logic = 0v 15 a electrical specifications v sa + = v a + = +5v, v sa - = v a - = -5v, t a = 25c, unless otherwise specified. (continued) parameter description conditions min typ max unit pin descriptions pin number el9111il pin name el9111il pin function EL9112il pin name EL9112il pin function 1 vsmo_b -5v to blue output buffer vsmo_b -5v to blue output buffer 2 vout_b blue output voltage referenced to 0v pin vout_b blue output voltage referenced to 0v pin 3 vspo_b +5v to blue output buffer vspo_b +5v to blue output buffer 4 vspo_g +5v to green output buffer vspo_g +5v to green output buffer 5 vout_g green output voltage referenced to 0v pin vout_g green output voltage referenced to 0v pin 6 vsmo_g -5v to green output buffer vsmo_g -5v to green output buffer 7 vsmo_r -5v to red output buffer vsmo_r -5v to red output buffer 8 vout_r red output voltage referenced to 0v pin vout_r red output voltage referenced to 0v pin 9 vspo_r +5v to red output buffer vspo_r +5v to red output buffer 10 vctrl equalization control voltage (0v to 1v) v ctrl equalization control voltage (0v to 1v) 11 vref reference voltage for logic signals, v ctrl and v gain pins vref reference voltage for logic signals, v ctrl and v gain pins 12 vgain_r red channel gain voltage (0v to 1v) v gain_r red channel gain voltage (0v to 1v) 13 vgain_g green channel gain voltage (0v to 1v) vgain_g green channel gain voltage (0v to 1v) 14 vgain_b blue channel gain voltage (0v to 1v) v gain_b blue channel gain voltage (0v to 1v) 15 vsm -5v to core of chip vsm -5v to core of chip 16 vinp_r red positive differential input vinp_r red positive differential input 17 vinm_r red negative differential input vinm_r red negative differential input 18 vinp_g green positive differential i nput vinp_g green positive differential input 19 vinm_g green negative differential i nput vinm_g green negative differential input 20 vinp_b blue positive differential input vinp_b blue positive differential input 21 vinm_b blue negative differential input vinm_b blue negative differential input 22 vsp +5v to core of chip vsp +5v to core of chip 23 hout decoded horizontal sync referenced to syncref vcm_r red common-mode voltage at inputs 24 vout decoded vertical sync referenced to syncref vcm_g green common-mode voltage at inputs 25 syncref reference level for h out and v out logic outputs vcm_b blue common-mode voltage at inputs el9111, EL9112
5 fn7450.1 may 17, 2005 26 x2 logic signal for x1/x2 output gain setti ng x2 logic signal for x1/x2 output gain setting 27 enable chip enable logic signal enable chip enable logic signal 28 0v 0v reference for output voltage 0v 0v reference for output voltage pin descriptions (continued) pin number el9111il pin name el9111il pin function EL9112il pin name EL9112il pin function typical performance curves figure 1. frequency response of all channels figure 2. gain vs frequency all channels figure 3. gain vs frequency for various v ctrl figure 4. gain vs frequency for various v ctrl & v gain 1m 10m 100m 200m 5 3 1 -1 -3 -5 x 2 =low v gain =0v v ctrl =0v r load =150 ? frequency (hz) gain (db) el9111, EL9112
6 fn7450.1 may 17, 2005 figure 5. gain vs frequency for various v ctrl & cable lengths figure 6. channel mismatch figure 7. group delay vs frequency for various v ctrl figure 8. output noise figure 9. offset vs v ctrl figure 10. dc gain vs v gain typical performance curves (continued) el9111, EL9112
7 fn7450.1 may 17, 2005 figure 11. common-mode rejectio n figure 12. cm amplifier bandwidth figure 13. (+)psrr vs frequency figure 14. (-)psrr vs frequency figure 15. blue crosstalk figure 16. blue crosstalk typical performance curves (continued) 100k 1m 10m 100m -10 -20 -40 -60 -80 -100 v gain =0.35v (all channels) v ctrl =0v x 2 =high frequency (hz) cmrr (db) 100k 1m 10m 100m 4 2 0 -2 -4 -6 v gain =0.35v (all channels) v ctrl =0v r load =150 ? x 2 =high frequency (hz) gain (db) 10 1k 100k 100m 0 -20 -40 -60 -80 -100 v cc =5v v ctrl =0v v gain =0v (all channels) inputs on gnd frequency (hz) +psrr (db) 100 10k 1m 10m 10 1k 100k 100m -20 -40 -60 -80 -100 -120 v ee =-5v v ctrl =0v v gain =0v (all channels) inputs on gnd frequency (hz) -psrr (db) 100 10k 1m 10m el9111, EL9112
8 fn7450.1 may 17, 2005 figure 17. green crosstalk figure 18. green crosstalk figure 19. red crosstalk figure 20. red crosstalk figure 21. rise time and fall time figure 22. pulse response for various cable lengths typical performance curves (continued) el9111, EL9112
9 fn7450.1 may 17, 2005 figure 23. total harmonic distortion figure 24. package power dissipation vs ambient temperature figure 25. package power dissipation vs ambient temperature typical performance curves (continued) jedec jesd51-3 low effective thermal conductivity test board 893mw j a = 1 4 0 c / w q f n 2 8 0 50 85 150 1.2 0.8 0.6 0.4 0.2 0 ambient temperature (c) power dissipation (w) 25 75 100 125 1 jedec jesd51-7 high effective thermal conductivity test board - qfn exposed diepad soldered to pcb per jesd51-5 j a = 3 7 c / w q f n 2 8 3.378w 0 50 85 150 4.5 3.5 2.5 1.5 0.5 0 ambient temperature (c) power dissipation (w) 25 75 100 125 4 2 1 3 el9111, EL9112
10 fn7450.1 may 17, 2005 applications information logic control the EL9112 has two logical input pins, chip enable (enable) and switch gain (x2). the logic circuits all have a nominal threshold of 1.1v ab ove the potential of the logic reference pin (vref). in most appl ications it is expected that this chip will run from a +5v, 0v, -5v supply system with logic being run between 0v and +5v. in this case the logic reference voltage should be tied to the 0v supply. if the logic is referenced to the -5v rail, then the logic reference should be connected to -5v. the logic reference pin sources about 60a and this will rise to about 200a if all inputs are true (positive). the logic inputs all source up to 10a when they are held at the logic reference level. when taken positive, the inputs sink a current dependent on the high level, up to 50a for a high level 5v above the reference level. the logic inputs, if not used, should be tied to the appropriate voltage in order to define their state. control reference and signal reference analog control voltages are required to set the equalizer and contrast levels. these signals are voltages in the range 0v - 1v, which are referenced to the control reference pin. it is expected that the control reference pin will be tied to 0v and the control voltage will vary from 0v to 1v. it is; however, acceptable to connect the cont rol reference to any potential between -5v and 0v to which the control voltages are referenced. the control voltage pins them selves are high impedance. the control reference pin will source between 0a and 200a depending on the control voltages being applied. the control reference and logic reference effectively remove the necessity for the 0v rail and operation from 5v (or 0v and 10v) only is possible. however we still need a further reference to define the 0v level of the single ended output signal. the reference for the output signal is provided by the 0v pin. the output stage cannot pull fully up or down to either supply so it is important that the reference is positioned to allow full output swing. the 0v reference should be tied to a 'quiet ground' as any noise on this pin is transferred directly to the output. the 0v pin is a high impedance pin and draws dc bias currents of a few a and similar levels of ac current. equalizing when transmitting a signal across a twisted pair cable, it is found that the high frequency (above 1mhz) information is attenuated more significantly than the inform ation at low frequencies. the attenuation is predominantly due to resistive skin effect losses and has a loss curve which depends on the resistivity of th e conductor, surface condition of the wire and the wire diam eter. for the range of high performance twisted pair cables based on 24awg copper wire (cat-5 etc.) these parameters vary only a little between cable types, and in general cables exhibit the same frequency dependence of loss. (the lower loss cables can be compared with somewhat longer lengths of their more lossy brothers.) this enables a single equalizing law equation to be built into the EL9112. with a control voltage applied between pins v ctrl and v ref , the frequency dependence of the equalization is shown in figure 8. the equalization matches the cable loss up to about 100mhz. above th is, system gain is rolled off rapidly to reduce noise bandwidth. the roll-off occurs more rapidly for higher control volt ages, thus the system (cable + equalizer) bandwidth reduces as the cable length increases. this is desirable, as noise becomes an increasing issue as the equalization increases. contrast by varying the voltage between pins v gain and v ref , the gain of the signal path can be changed in the ratio 4:1. the gain change varies almost linearly with control voltage. for normal operation it is ant icipated the x2 mode will be selected and the output load will be back matched. a unity gain to the output load will then be achieved with a gain control voltage of about 0.35v. this allows the gain to be trimmed up or down by 6db to compensate for any gain/loss errors that affect the contrast of the video signal. figure 26 shows an example plot of th e gain to the load with gain control voltage. figure 26. variation of gain with gain control voltage c ommon mode sync decoding the el9111 features common mode decoding to allow horizontal and vertical synchronization information, which has been encoded on the three differential inputs by the el4543, to be decoded. the entire rgb video signal can therefore be transmitted, along with the associated synchronization information, by using just three twisted pairs. 00.8 v gain 0.4 1 2 1.8 1.4 1 0.6 0.4 gain (v) 0.6 0.2 1.6 1.2 0.8 el9111, EL9112
11 fn7450.1 may 17, 2005 decoding is based on the el4543 encoding scheme, as described in figure 27 and table 1. the scheme is a three- level system, which has been de signed such that the sum of the common mode voltages results in a fixed average dc level with no ac content. this eliminates the effect of emi radiation into the common mode signals along the twisted pairs of the cable the common mode voltages are initially extracted by the el9111 from the three input pa irs. these are then passed to an internal logic decoding block to provide horizontal and vertical sync output signals (h out and v out ). figure 27. h & v syncs encoded table 1. h and v sync decoding red cm green cm blue cm h sync v sync mid high low low low high low mid low high low high mid high low mid low high high high note: level ?mid? is halfway between ?high? and ?low? time (0.5ms/div) voltage (0.5v/div) blue cm out (ch a) green cm out (ch b) red cm out (ch c) v sync h sync voltage (2.5v/div) el9111, EL9112
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7450.1 may 17, 2005 package outline drawing note: the package drawing shown here may not be the latest version. to check the latest revision, please refer to the intersil w ebsite at http://www.intersil.com/design/packages/index.asp el9111, EL9112

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